Synopsys VCS Commands for Verilog Compilation

For simple designs the major steps are:

1. Compile the design
2. Run the Simulation
3. Generate Code Coverage Report

Compiling Verilog design using VCS

vcs -lca -cm line+cond+fsm+tgl+path+assert -cm_line
contassign -cm_cond allops+anywidth+event -cm_noconst
-debug_all +v2k -PP +lint=all -Mupdate -l vcs.log -f list.f

Included Options

• -cm coverage-type: specifies the type of coverage information to collect. The line, tgl, cond, fsm and path options enable statement (line), toggle, condition, FSM, and path coverage respectively. Any combination of coverage can be enabled simultaneously using the + sign e.g. -cm cond+line enables conditional and line coverage.
• -cm_line contassign: monitor continuous assignments for line coverage
• -cm_cond allops+anywidth+event: monitor non-logical operators, of any width, and always block sensitivity expressions for condition coverage
• -cm_noconst: try to automatically ignore constant expressions and unreachable statements
  for line and condition coverage
• +lint=all: turns on all verilog warnings
• +v2k: tells VCS to handle Verilog-2001 features, include this option if you are using those features
• -PP: turns on support for using the VPD trace output format
• -debug_all option allows to run the interactive DVE tool and use steps to debug the design
• -l file_name: logs the compiler messages to given file name
• -f file_name: tells VCS to read source files from the given file

Few optional arguments

• -sverilog: include this options if system verilog source files are also present. This enables compilation for system verilog source files.
• -v: use this flag to indicate which verilog files are part of the library and thus be compiled if needed.
• -timescale: can be used to specify how the abstract delay units in their design map into real time units e.g. -timescale=1ns/10ps

During compilation a subdirectory named csrc is created to store the files generated by compilation. This directory includes:

• Makefile for the compilation process
• Object files from the compilation. These object files are linked to create the simv executable.
• Intermediate C or Assembly source files.

Incremental Compilation

The source files are compiled on module-by-module basis. Incremental compilation means that if we run the vcs command again, only the modules that have changed after the last compilation are recompiled. VCS compares the modules in the source file to the descriptor information in the generated files from the last compilation, if a module’s contents are different from what VCS recorded in the last compilation, VCS recompiles the module.

Compile time options that affect incremental compilation all begin with -M.

Running the Simulation

For text based output use:

./simv

For debugging with DVE GUI use:

./simv -gui

For Generating code coverage information run as:

./simv -cm line+cond+fsm+tgl+assert+path

Generating code coverage reports using VCS URG

For generating code coverage report in html form use the following command

urg -lca -dir simv.vdb

To generate code coverage report in text form add the extra options as

 urg -lca -dir simv.vdb -show text

A directory named urgReport will be created in current directory. This directory contains all the generated reports.

References

• Successful Mixed language code coverage with VCS
• VCS Quickstart
• VCS User Guide

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